Silicon Design Engineer 4
Remote CONTRACT Job Opportunity based in Redmond, WA. Candidates must be based in PST time zone to be considered for this role... Purpose of the Team: The purpose of this team is create custom silicon . Key projects: This role will contribute to with some IPs going into some chips for products- generating fabric, stitching together, connecting modules. Typical task breakdown and operating rhythm: The role will consist of 20% meetings and 80% coding. What makes this role interesting? - This role provides the opportunity to work on cutting edge technology for next products. Candidate Requirements Years of Experience Required: 8+ years of experience in hardware design Degrees or certifications required: Bachelors degree in Electrical Engineering, Computer Engineering, or related degree required to be eligible for this role. Disqualifiers: Candidates with constant job hopping (need to be able to stick out the contract), lack of recent experience of the sub system integration or building fabrics will not be eligible for the role. Best vs. Average: The ideal resume would contain strong knowledge in fabric and ARM architecture. Top 3 Hard Skills Required + Years of Experience Minimum 3+ years of Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol. Minimum 3+ years with Knowledge of the ARM architecture. Minimum 7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure.
Summary
Front-End Silicon Design Engineer who is responsible for front end design tasks at the block and sub-system levels. These tasks include RTL design, sub-system integration, RTL generation via 3rd party tools, and repository management. Job Responsibilities Responsible for various integration tasks at the block level Responsible for various integration tasks at the sub-system level Responsible for generation of cores (Cadence Tensilica) Responsible for the generation and integration of NOCs (Synopsys and Arteris) Manage repos for shared collateral across design teams Skills Knowledge of the ARM architecture Knowledge of Cadence Tensilica cores Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol Worked with leading-edge technologies 5 nm or smaller. Knowledge of GIT repositories Education/Experience Bachelors degree in Electrical Engineering, Computer Engineering, or related degree required. 8+ years of experience in hardware design 7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure. About Actalent Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. Diversity, Equity & Inclusion At Actalent, Diversity And Inclusion Are a Bridge Towards The Equity And Success Of Our People. DE&I Are Embedded Into Our Culture Through Hiring diverse talent Maintaining an inclusive environment through persistent self-reflection Building a culture of care, engagement, and recognition with clear outcomes Ensuring growth opportunities for our people The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law. If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [email protected] for other accommodation options Apply Job!